As is well known, a phase-locked loop system produces an output signal which tracks an input signal in frequency and exhibits a fixed phase relationship to the input signal. As the input signal changes in frequency, the output signal likewise changes in such a manner as to maintain the phase relationship between the input and output signals. Originally, phase-locked loops were implemented using only analog techniques. These techniques continue in use today in many data processing and communications systems. An analog phase-locked loop typically consists of four fundamental parts; namely, a phase detector, a charge pump, a filter and a voltage controlled oscillator (VCO).
The phase detector is a device which detects the difference in phase between two input signals, and produces an output signal proportional to the amount of the phase difference. In a phase-locked loop the two inputs to the phase detector are the input to the phase-locked loop and the output signal of the VCO, i.e., the output of the phase-locked loop. The output signal from the phase detector is an analog up/down signal, the magnitude of which is representative of the amount of phase difference between the two input signals thereto, hereinafter referred to as an error signal. The charge pump produces a control voltage based on this error signal and outputs the control voltage to the filter, which is disposed at the input of the VCO. The filter serves to remove any high frequency components from the error signal produced by the charge pump and provides a slowly varying output signal which is representative of the average error in phase between the output signal and the input signal.
The voltage controlled oscillator is an analog oscillator which generates an output signal having a frequency corresponding to the slowly varying control signal across the filter. In one conventional embodiment, the voltage controlled oscillator comprises a voltage to current converter which is coupled through a summing node to an oscillator that provides the output signal from an input current. Often, a fixed bias current is also fed to the summing node. The fixed bias current operates to moderate the gain characteristics of the VCO.
Due to the feedback of the output signal to an input of the phase detector, the frequency of the voltage controlled oscillator is adjusted by the VCO input signal, i.e., the control signal across the filter, to maintain the fixed relationship between the input signal and output signal of the PLL.
Component tolerances and process variations often result in a wide range of possible center frequency settings at the VCO-output of an analog phase-locked loop system. Precise setting of a center frequency notwithstanding component tolerances of a PLL has traditionally been attempted by trimming the value of a resistor(s) within the VCO. This is a difficult and expensive operation, and still requires circuits which are very temperature stable and insensitive to power supply variations. The gain of a phase-locked loop can also vary significantly with process, temperature and power supply variations. Further, due to technology advances, PLLs are required to produce higher frequencies today while VCO transfer function tolerances become more critical and less achievable simultaneously.
As the density of digital circuitry increases, digital methods for controlling analog circuits become more feasible. The calibration systems and methods presented herein result in an analog PLL with, for example, a zero tolerance center frequency and/or minimal VCO gain deviation across the transfer function, which means a more practical and commercially viable PLL.